Study Sections C.3 and C.4 of your text and pay close attention to the differences between how the State register is imp

[answerhappygod]

Study Sections C.3 and C.4 of your text and pay closeattention to the differences between how the State register isimplemented in Figure C.3.2 and that of the Address selectlogic depicted in Figures C.4.1 and C.4.2.1) How many lines should AddrCtl have?2) When AddrCtl enables the MUX, in Figure C.4.2, tomultiplex to line 3 that feeds into the State box, what will theState box do? How can such action be implemented based onwhat we have discussed so far from our lectures?
what do you mean none?

Study Sections C 3 And C 4 Of Your Text And Pay Close Attention To The Differences Between How The State Register Is Imp 1 (48.95 KiB) Viewed 42 times

Study Sections C 3 And C 4 Of Your Text And Pay Close Attention To The Differences Between How The State Register Is Imp 2 (53.72 KiB) Viewed 42 times

Study Sections C 3 And C 4 Of Your Text And Pay Close Attention To The Differences Between How The State Register Is Imp 3 (26.57 KiB) Viewed 42 times

Control logic Inputs Instruction register opcode field Outputs State register PCWrite PCWriteCond lorD MemRead MemWrite IRWrite MemtoReg PCSource ALUOP ALUSrcB ALUSICA RegWrite RegDst NS3 NS2 NS1 NSO FIGURE C.3.2 The control unit for LEGV8 will consist of some control logic and a register to hold the state. The state register is written at the active clock edge and is stable during the clock cycle.
Control unit Adder PLA or ROM Input State Address select logic Op[5-0] Outputs Instruction register opcode field PCWrite PCWrite Cond lorD MemRead MemWrite IRWrite MemtoReg PCSource ALUOP ALUSrcB ALUSrCA RegWrite RegDst AddrCtl FIGURE C.4.1 The control unit using an explicit counter to compute the next state. In this control unit, the next state is computed using a counter (at least in some states). By comparison, Figure C.3.2 encodes the next state in the control logic for every state. In this control unit, the signals labeled AddrCtl control how the next state is determined.
Adder PLA or ROM State Mux 3210 Dispatch ROM 2 Dispatch ROM 1 Instruction register opcode field Address select logic AddrCtl FIGURE C.4.2 This is the address select logic for the control unit of Figure C.4.1.