Problem 5 (20 points) Anwer the following question regarding registers and sequential circuits (10 points) Considera uni

[answerhappygod]

Problem 5 20 Points Anwer The Following Question Regarding Registers And Sequential Circuits 10 Points Considera Uni 1 (47.8 KiB) Viewed 20 times

Problem 5 (20 points) Anwer the following question regarding registers and sequential circuits (10 points) Considera universal shift register with the functionality shown in the table below: Mode contral Register operation Parallel Lead Shift leb No Change The registeret synchronously to all 0's when clear is set to clear 1. All other functions and positive edge triggered Assame the following inputs Parallel inputs: (left-most bit), Z-1, 4-0, A-1 (right-most bit) Serial input for right-shift- Serial input for left-shift-1 Register vakar att, o Registrats Assame that the register is initially loaded with all I's. What is the register value for the instances in time, ... marked in the following timing diagram? Register valuatis Register valuati Registrati % 0 Register 0 to (10 points) Modify the circuit diagram below by adding a four-inque NAND gate to the signals Ai, As, Aiễ² and As, and connecting the output of the NAND gate the "Reset line S . After renegative clock adga • After four negative clock edges • After five negative clock edges: A periodic clock signal is connected to the Count inque. Assuring the initial flip-flop state AAAA-1010 when the clock is high, determine the circuit output for these two cas Original with NAND 1010 AAAA_1____010 . After the next negative clock alge AAAA- . After two negative clock edges AAAA AAAA AAA- AAAA Your answers should assure that all transients occurring after the clock edge have settled down, ie that the output has stabilized to its firal value for the clock cycle of interest.