Q3. Show the micro-operations and control signals in the same fashion as Table 19.1 for the processor in Figure 19.5 for the following instructions: Load Accumulator Store Accumulator Add to Accumulator Jump Cs -94-C₁1 AC ALU هت C12 81 M R M R PC -C3 04-C₂ IR -C₁ C6- C13 C10 G- Control unit Flags Clock Control signals Figure 19.5 Data Paths and Control Signals Control signals
Active Control Signals C₂ C5, CR C₁ Cg C₁, CR C₁ C₁ C12, Cw Table 19.1 Micro-operations and Control Signals Micro-operations t₁: MAR - (PC) Fetch: t₂: MBR - Memory PC (PC) + 1 t3: IR - (MBR) t₁: MAR (IR(Address)) Indirect: t₂: MBR - Memory t3: IR(Address)← (MBR(Address)) t₁: MBR - (PC) t₂: MAR Save-address Interrupt: PC -Routine-address t3: Memory (MBR) CR = Read control signal to system bus. Cw = Write control signal to system bus.
Q3. Show the micro-operations and control signals in the same fashion as Table 19.1 for the processor in Figure 19.5 for
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Q3. Show the micro-operations and control signals in the same fashion as Table 19.1 for the processor in Figure 19.5 for
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