- 08 Design For The S R Latch Assume Each Nand Gate Has A Delay Of 1 Nsec The Inputs To The S R Latch Are Applied As Fo 1 (62.16 KiB) Viewed 24 times
08. Design For the S-R latch, assume each NAND gate has a delay of 1 nsec. The inputs to the S-R latch are applied as follows. At every 1 nsec, the value at S is given by 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1. At every 1 nsec, the value at R is given by 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1. Find out the waveform at the outputs, Q, Q' as functions of time. 5° R Page 1 of 2 Q9. Now assume that the top NAND gate has a delay of 1 nsec, while the bottom NAND gate has a delay of 2 nsec. Rework the above problem.