- A 2 Tlb And Cache Based On A Previous Final Exam Question You Are Designing A Paged Memory System For A High Performance 1 (50.37 KiB) Viewed 37 times
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A.2 TLB and Cache based on a previous final exam question You are designing a paged memory system for a high-performance 16-bit embedded processor. The initial virtual memory subsystem design has the following characteristics: . 16-bit virtual address • 30-bit physical address, with 1 GiB physical memory always installed • 4 KiB page size • 8-entries, 2-way set associative TLB (i.e. 4 rows with 2 sets each), true LRU • A single linear page table for each user process • Page fault penalty: 7000 cycles • On TLB hit and cache hit, combined TLB and cache access takes 1 cycle • Page tables are not cached • Single level cache: physically tagged, direct map, 4 word line size, 1 MiB capacity, • Cache hit time: 1 cycle • Cache miss penalty: 400 cycles
A.2.1 Answer the following: 1 Number of bits needed for a virtual page number bits N Number of bits needed for a physical page number bits 3 Number of bits needed for page offset bits 4 Number of lines in the cache 5 Size of a tag for each line of the cache bits A.2.2 [3 pts) What is the TLB reach of the system? A.2.3 After profiling a program B, you found that out of all the memory accesses, 7% results in TLB MISS. Among the misses, 1% results in a page fault. As a result of these address translations, what is the average memory access time (in cycles) for B? A.2.4 You found that in general the data cache has a miss rate of 5%. Your processor always complete address translations before accessing the data cache. That is, the system handles any TLB misses or