D Table 26 Shows The Instruction Specification Of All The Instructions Supported By The Microprocessor Shown In Figure 1 (140.4 KiB) Viewed 40 times
(d) Table 26 shows the instruction specification of all the instructions supported by the microprocessor shown in Figure Q6(a) and Figure Q6(b). Figure Q6(c) shows a piece of an assembly language program. (i) What is the effective address generated by the Load instruction at address 200? (1 mark) (ii) What is the effective address generated by the Load at address 201? (1 mark) (iii) What will be the data in registers R1 to R3 after executing the instructions from 200 to 203? (2 marks) (iv)The four instruction formats supported by the microprocessor are shown in Figure Q6(d). Assume that the code for registers R0 to R3 are (000)2 to (011)2. Convert the assembly language codes at addresses 200, 201, 203 and 204 in Figure Q6(c) into the machine language codes. (4 marks) (v) Deduce the 16-bit control vector required for the instructions at addresses 200, 203 in Figure Q6(c). Give your answers according to the following format. (6 marks)
Dulapur ALU, ALU, ALU, 0 0 0 Operation Pass through A AND B O 0 0 1 0 1 0 A ORB 0 1 1 MA 11-12 WAT RE RE RRE KN 1 0 0 AR 10 Chat 1 0 1 A-R 16- 1 0 A+1 7-6+ 1 1 A-1 MU, ALU ALU AL (b) 16 SH Shifter SH. SH SH. 0 0 Z.N - OE 0 1 Operation Pass through Shift left and fill with o Shift right and fill with o Rotate right 1 O 1 1 Dulu Output WE WA X Operation No operation InPort RO 00 ----- 16 In Port WE WA Che -WA 4 x16 RAE Register File RRE -RAA, RRA -RAA Part RRA- A R 16 116 01 InPort => RI | | 1 10 In Port R2 Part 11 InPost RAI RAA. RBK Operation Operation OA RIA X 0 X 0 1 00 ROA 1 00 4 - || . 01 RIA 1 01 RIB 1 10 R2A 1 10 R211 1 11 13 A 11 131 Figure Q6(b)
PC 0 Instructions JUMP 200 Comments % The program starts at 200 . 198 199 200 201 200 300 LOAD R3,-2 LOAD R2 199 202 SUBR RI, R3, R2 JN 3 203 204 205 206 207 : : JUMPO Figure Q6(C) 15 Opcode 98 65 3 2 0 Destination Source register Source register 2 register (RD) (RSI) (RS2) Register 15 0 Opcode 98 65 3 2 Destination Source register register (RD) (RS) Immediate Operand (OP) 15 Opcode 15 98 6 5 Register (RD) or don't care Address (AD) Jump and Branch 98 65 3 2 0 Addressing Offset (Off) or Register (RD) Mode (Mo) don't care Load and Store Figure Q6(d) Opcode
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