- T Flip Flop T Flip Flop Is A Complementing Flip Flop Experiments I Sr Latch Nor Latch 1 Draw The Schematic For A Nor 1 (120.5 KiB) Viewed 32 times
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T Flip-flop T Flip-flop is a complementing flip-flop. Experiments I. SR Latch-NOR latch 1. Draw the schematic for a NOR latch in the space below. Using a data sheet for a 7402 IC, mark the pin numbers on the schematic that will be used to construct a circuit. VCC GND 7402 Quad 2 Input NOR 2. Construct the NOR latch on a breadboard. Using logic switch for the inputs (S, C) and LED indicator for Q and 7. Place the S &C inputs a logic “O” initially. Record the pin # for S ,Q , and ē 3. Turn on the power supply. Record the outputs. Q= 0 = What is the state of latch? 4. If 'Q' is a logic 'l', toggle the 'C' input to a logic ‘l’and then back to a '0'. f'Q' is a logic '0', then go to procedure 5. 5. Set the 'S' input to a logic ‘l’, record the state of the outputs. Q= what is the state of latch? 2
J-K Flip-Flop The operation of the J-K flip-flop is similar to the S-C latches described above, except that it does not have an invalid state. The invalid state is replaced with a TOGGLE state, which causes the output (Q) to change logic levels. The state of the flip-flop is determined by the value of the J and K inputs when the specified clock edge is detected. This flip-flop may also have asynchronous PRESET and CLEAR inputs. The asynchronous inputs can be used to change the state of the flip-flop regardless of the state of the synchronous inputs. The inputs can either be active-low or active-high depending upon the device type. D Flip-Flop The logic level of the input (D) will be transferred to the output (Q) when the specified clock edge is detected. This device may also have asynchronous PRESET and CLEAR inputs. The asynchronous inputs can be used to change the state of the flip-flop regardless of the state of the synchronous inputs. The inputs can either be active-low or active-high depending upon the device type T Flip-flop T Flip-flop is a complementing flip-flop. Experiments I. SR Latch-NOR latch 1. Draw the schematic for a NOR latch in the space below. Using a data sheet for a 7402 IC, mark the pin numbers on the schematic that will be used to construct a circuit. VCC GND and © 7402 Quad 2 Input NOR 2. Construct the NOR latch on a breadboard. Using logic switch for the inputs (S, C) and LED indicator for Q and 6. Place the S&C inputs a logic "0" initially. Record the pin #fors 3. Turn on the power supply. Record the outputs. 0 What is the state of latch? 4. If Q' is a logic '1', toggle the 'C' input to a logic 'l' and then back to a '0'. f*Q® is a logic 'o', then go to procedure 5. 5. Set the 'S' input to a logic '1', record the state of the outputs. Q= . what is the state of latch? 2
answer 6. Return the 'S' input back to a logic '0', what effect did this have on the outputs? Explain your 7. Set the 'C' input to a logic '1'. Record the state of the outputs. . what is the state of latch? Check by instructor II. SR Latch-NAND latch 1. Draw the schematic for a NAND latch in the space below. Using a data sheet for a 7400 IC, mark the pin numbers on the schematic that will be used to construct a circuit. VCC pl GND 7400 Quad 2 Input NAND 2. Construct the NAND latch on a breadboard. Using logic switch for the inputs (S, C) and LED indicator for Q and ©. Place the S&C inputs a logic "O" initially. Record the pin #for and © 3. Turn on the power supply. Record the outputs. 0 What is the state of latch? 4. If Q' is a logic '1', toggle the 'C' input to a logic 'l' and then back to a 'o'. If 'Q' is a logic '0', then go to procedure 5. 5. Set the 's' input to a logic '1', record the state of the outputs. Q= o= what is the state of latch now? 6. Return the 'S' input back to a logic '0', what effect did this have on the outputs? Explain your 7. Set the 'C input to a logic *1'. Record the state of the outputs. Q= what is the state of latch now? answer Check by instructor 3
III. D Flip-Flop Procedure: 1. Refer to the 7474 IC chip pin diagram to mark the pin numbers to the following figure. Wire the asynchronous inputs CLR and PRE to logic switches S7 and 58. Wire the synchronous inputs to the logic switch S1 and the CLK input to a debounced pushbutton PB1. Wire the output Q and to the LED indicator Ll and L2. 2. Operate the asynchronous inputs CLR and PRE according to the inputs in Table 1, and record the results in the table. Also write the name of the condition in the last column of the table. 3. Disable the asynchronous inputs by setting PRE and CLR Operate the synchronous inputs D and CLK of the 7474 according to the inputs in Table 2. What does t in clock column mean? _.Observe and record the results in Table2. Table 1 Kayaches taputo CLE PS O O Inputs Preset Clear Q Outputs Name of Condition Prohibited de ed 0 0 1 1 0 1 0 1 D y pets . FF cik Clear Q to 0. Preset Q to 1 Disable asynchronous inputs I cir Table 2 Inputs Clock Data CLK D 1 0 1 0 1 1 1 1 Outputs Before Clock Pulse After Clock Pulse Q Q O 0 1 0 1 0 1 1 0 Questions answer on your report) 1) Draw a logic symbol for a D flip-flop. Label the inputs D, CLK, PR, and CLR and the outputs Q and Q. 2) What are the synchronous inputs of the D flip-flop? 3) What are the asynchronous inputs of the D flip-flop? 4) Which output column in Table 2 is exactly the same as the input D column? 5) A logical at PRE will preset the output of the 7474 D flip-flop to a logical assuming that CLR is a l. 6) The synchronous inputs of the D flip-flop only operate when the PR and CLR inputs are (disabled, enabled) with a logical 7) The 7474 D flip-flop is a (negative-, positive-) edge triggered flip-flop. 8) Write the state/characteristic equation of D flip flop, i.e., Q(t+1)= ? a 4
Lynchos Input CLR PS O IV. JK Flip-Flop: 1. Refer to the 7476 IC chip pin diagram to mark the pin numbers to the right figure. 2. Wire the asynchronous inputs CLR and PRE to logic switches S7 and S8. Wire the synchronous inputs J&K to the logic switch S1 & S2. Wire the CLK input to a debounced pushbutton PBI. Wire the output Q and © to the LED indicator Ll and L2. 3. Operate the asynchronous inputs PRE and CLR and record the results in Table 3. Also, write the condition in the last column. 4. Operate the synchronous inputs J, K, and CLK of the 7476 according to Table 4. Observe and record results. What does t in clock column mean? Synche luta 98 ou pe J Q PF D CLK K II K slr Table 3 Table 4 Inputs Preset Clear Inputs Clock Data Outputs After Clock Pulse Before Clock Pulse Outputs Name of Q5 Condition Prohibited Nause of Condation CLK J K K Q ē © Q © 0 0 1 1 0 1 0 1 0 0 0 1 + 0 1 0 1 1 0 0 1 Clear Q to 0. Preset Q to 1 Disable asynchronous inputs + + + + + + 1 1 0 1 0 1 0 oo 1 1 0 0 1 0 + 1 1 1 0 hold, reset, set, or toggle Questions answer on your report) 1) Draw a logic symbol for a J-K flip-flop. Label the inputs J, K, CLK, PRE, and CLR and the outputs Q and Q: 2) What are the synchronous inputs of the J-K flip-flop? 3) What are the asynchronous inputs of the J-K flip-flop? 4) The truth table for the asynchronous inputs is the same as for what other flip-flop we have used? 5) The inverter bubbles at the PRE and CLR inputs of the 7476 mean that a logical will disable these asynchronous inputs and enable the synchronous inputs. 6) What is the meaning of the inverter bubble on the clock input of the 7476? 7) What is meant by the "toggle" position of the flip-flop (i.e., what happens to the LED's in toggle mode)? Also, what must PRE, CLR, J, and K be in order for the FF to be in toggle mode? 8) Write the state/characteristic equation of JK flip flop, i.e., Q(t+1)= ? 9) What type of triggering does the 7476 use (positive or negative edge)? 5
V. T-Flip-Flop T flip-flop is a complementing flip-flop and can be obtained from JK flip-flop or D flip-flop as below. Construct a T flip-flop and record its behavior in the following table. 1 D PC к DC (a) From IK flip flop (b) From D flip flop (e) Graphic symbol Fig. 5-13 T Flip-Flop Q(t) Q(t+1) Clock T Name of Condition 0 0 0 1 1 0 1 1 Write the state/characteristic equation of T flip flop, i.e., Q(t+1) = ? Demonstrate your working circuit to instructor:
answer 6. Return the 'S' input back to a logic '0', what effect did this have on the outputs? Explain your 7. Set the 'C' input to a logic '1'. Record the state of the outputs. . what is the state of latch? Check by instructor II. SR Latch-NAND latch 1. Draw the schematic for a NAND latch in the space below. Using a data sheet for a 7400 IC, mark the pin numbers on the schematic that will be used to construct a circuit. VCC pl GND 7400 Quad 2 Input NAND 2. Construct the NAND latch on a breadboard. Using logic switch for the inputs (S, C) and LED indicator for Q and ©. Place the S&C inputs a logic "O" initially. Record the pin #for and © 3. Turn on the power supply. Record the outputs. 0 What is the state of latch? 4. If Q' is a logic '1', toggle the 'C' input to a logic 'l' and then back to a 'o'. If 'Q' is a logic '0', then go to procedure 5. 5. Set the 's' input to a logic '1', record the state of the outputs. Q= o= what is the state of latch now? 6. Return the 'S' input back to a logic '0', what effect did this have on the outputs? Explain your 7. Set the 'C input to a logic *1'. Record the state of the outputs. Q= what is the state of latch now? answer Check by instructor 3