28. How many errors does the following verilog module code have? module something ( input a, input b, input c, output re

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28 How Many Errors Does The Following Verilog Module Code Have Module Something Input A Input B Input C Output Re 1 (2.05 MiB) Viewed 20 times

28. How many errors does the following verilog module code have? module something ( input a, input b, input c, output reg d ); I always @ (posedge a) begin if (c) begin d <= 1'60; end else begin d = b; end end endmodule (a) 3 (b) 2 (c) 1 (d) 0 29. A verilog XOR gate has one input signal of logic Z and the other input signal of logic 1. The output will be (a) x (b) X (c) z (d) 1