28. What is common name for the circuit implemented by the following verilog code? module something (a,b,c,d,e,f); input

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28 What Is Common Name For The Circuit Implemented By The Following Verilog Code Module Something A B C D E F Input 1 (349.34 KiB) Viewed 29 times

28. What is common name for the circuit implemented by the following verilog code? module something (a,b,c,d,e,f); input b, c, d, e, f; output 17:0] a; reg (7:0) a; always @ (posedge b) begin if (c) begin a <= 8'do ; end else if (d) begin case (e) 0: a <= {a[6:0), f); 1: a <= {f, a[7:1]); endcase end else begin a <= a; end end endmodule (a) parallel in serial out register (b) bidirectional shift register (c) linear feedback shift register (d) priority shift register 29. Upon synthesis, will a variable declared as a reg in an always@(clk) procedure generate flip-flops? a (a) no (b) maybe (c) yes, always (d) yes, if there is no reset signal ifall colutions were possible which