6. A verilog XOR gate has one input signal of logic Z and the other input signal of logic 1. The output will bec (a) 1 (

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6. A verilog XOR gate has one input signal of logic Z and the other input signal of logic 1. The
output will bec
(a) 1 (b) 2
(c) X
(d) X
7. we like to the clock gating to:
(a) decrease tastability MTIF
(b) decrease power consumption (c) decrease clock alew
(d) decrease hold time violations
8. If a D Hip-flop has a negative hold time which of the following statements are true?
(a) all answers are correct
(b) any circuits using these flip-flops cannot have hold time violations (e) if the d input changes after the setup time the output will be synchronous
(d) if the d input changes at the clock edge the output will be synchronous
please solve this with in 30 minuts please solve All parts