1 Library ieee; 2 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; 4 5 pentity miniproject is 6 port(x : in

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1 Library Ieee 2 Use Ieee Std Logic 1164 All Use Ieee Std Logic Unsigned All 4 5 Pentity Miniproject Is 6 Port X In 1 (29.16 KiB) Viewed 20 times

1 Library ieee; 2 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; 4 5 pentity miniproject is 6 port(x : in std_logic_vector (7 downto 0); 7 OPER: in std_logic; 8 z.: out std_logic_vector (7 downto 0)); Lend miniproject;, 10 qarchitecture archi of miniproject is 11 constant Y: std_logic_vector ( 7 downto 0 ) := "00110110" ; 12 © begin 13 Z <= x + y when OPER='0' else X - Y; 15 end archi; 14